The present invention relates to a storage device and a storage method and, for example, relates to a storage device that stores a status flag and a storage method.
A complementary read flash memory is known as described in, for example, Japanese Unexamined Patent Application Publication No. 2008-117510. In the complementary read flash memory, two rewritable nonvolatile memory cells form a pair, and 1-bit information is stored in the one pair of memory cells (which can be also referred to hereinafter as a twin cell). The cells that constitute the twin cell can be in either a low threshold voltage state or a high threshold voltage state. The low threshold voltage state is a state where a threshold voltage (Vth) of a transistor that forms a cell is lower than a specified reference value. The high threshold voltage state is a state where a threshold voltage (Vth) of a transistor that forms a cell is equal to or higher than the specified reference value.
In the complementary read flash memory, information is stored by setting two memory cells that form a twin cell to threshold voltage states different from each other. Specifically, for example, a value of “0” is stored when a first memory cell of a twin cell is in the high threshold voltage state and a second memory cell of the twin cell is in the low threshold voltage state. On the other hand, a value of “1” is stored when the first memory cell is in the low threshold voltage state and the second memory cell is in the high threshold voltage state. Further, when both the first memory cell and the second memory cell are in the low threshold voltage state, they are in an erased state (which is also called an initialized state). In the case of the erased state, a read result from the twin cell is undefined. Specifically, a read value can be “1” or can be “0”, which is not a uniquely defined value.